Tzung-Han Juang

Hi! I am a PhD Candidate in the Department of Electrical and Computer Engineering (ECE) at McGill University.

My PhD is supervised by Christophe Dubach.

My current project focuses on high-level hardware generation of neural network accelerators on Field Programmable Gate Array (FPGA) devices. Our approaches are based on functional intermediate representations (IRs), which provide a convenient way to express parallelism and data dependency. I am also interested in topics related to Hardware Design, Compilers, and Machine Learning.

My previous projects include reinforcement learning for production line management (at Northwestern University) and hardware design for convolutional neural network accelerators (at National Taiwan University). I also had summer internships at Intel (for code optimization and machine learning) and Mediatek (as a hardware engineer).

Education

PhD in Electrical and Computer Engineering, McGill University, Canada (Current)
MSc in Computer Science, Northwestern University, USA (2020)
MSc in Electronic Engineering, National Taiwan University, Taiwan (2018)
BS in Electrical Engineering, National Cheng Kung University, Taiwan (2016)

Internships

Data Science Intern, Intel, Arizona, USA (2020/06-2020/09)
Hardware Engineering Intern, Mediatek, Taiwan (2016/06-2016/08)

Publications

Let Coarse-Grained Resources Be Shared: Mapping Entire Neural Networks on FPGAs [Paper] [Poster] [Slide]
Tzung-Han Juang, Christof Schlaak, and Christophe Dubach
(Best Paper Award Candidate) ACM Transactions on Embedded Computing Systems (TECS), vol. 22, 5s, no. 114, presented at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems 2023 (CASES'23)
Optimizing Data Reshaping Operations in Functional IRs for High-level Synthesis [Paper]
Christof Schlaak, Tzung-Han Juang, and Christophe Dubach
In Proceedings of the 23rd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES) 2022, page 61-72, New York, NY, USA, 2022
Memory-aware Functional IR for Higher-level Synthesis of Accelerators [Paper]
Christof Schlaak, Tzung-Han Juang, and Christophe Dubach
ACM Transactions on Architecture and Code Optimization (TACO), vol. 19, no. 2, Jan 2022

Presentations and Posters

Automatic Shareable Function Detection for Hardware Accelerator Synthesis with Functional IRs
Tzung-Han Juang, Christof Schlaak, and Christophe Dubach
Student Research Competition at ACM International Symposium on Code Generation and Optimization (CGO), Montreal, Canada, 2023
Coarse-Grained Resource Sharing for Entire Neural Networks [Slide]
Tzung-Han Juang, Christof Schlaak, and Christophe Dubach
1st Languages, Architectures, and Tools for Heterogeneous Computing (LATHC) Workshop, Montreal, Canada, Feb 2023
Data Reshaping and Function Reusing for High-Level Synthesis with Functional IR
Tzung-Han Juang, Christof Schlaak, and Christophe Dubach
19th Compiler-Driven Performance (CDP) Workshop, Toronto, Canada, Nov 2022
Design Space Exploration of Function Reusing in Functional IRs for Accelerator Generation [Poster]
Tzung-Han Juang, Christof Schlaak, and Christophe Dubach
50th anniversary of the McGill School of Computer Science, Montreal, Canada, Oct 2022

Teaching

Computer Organization, Tutor, McGill University (Fall 2023)
Compiler Design, Tutor, McGill University (Winter 2023)
Computer Organization, Tutor, McGill University (Fall 2022)
Integrated Circuit Design Lab, Tutor, National Taiwan University (Spring 2018)
Integrated Circuit Design, Marker, National Taiwan University (Fall 2017)
Integrated Circuit Design Lab, Tutor, National Taiwan University (Spring 2017)

Contact: tzung-han.juang at mail.mcgill.ca